1. Field of the Invention
The present invention relates to a voltage comparator and a parallel type or a successive approximation type analog-to-digital converter using same.
2. Description of the Related Art
An analog-to-digital converter (hereinafter referred to as an ADC) converts the level of an input analog signal to a digital signal. In general, there are two types of ADCs--a parallel type and a successive approximation type. In any ADC, a voltage comparator is provided for comparing the voltages of the analog signal and a reference signal. As one example of the voltage comparator, there can be mentioned a differential type voltage comparator. The differential type voltage comparator compares the magnitudes of the differential voltage of the reference signal and the differential voltage of the differential input signal and sets the level of the output signal in accordance with the result of the comparison.
FIG. 1 is a circuit diagram of the configuration of a parallel type ADC of the related art. This parallel type ADC is constituted by a plurality of resistors R.sub.1 to R.sub.15 connected in series, differential type voltage comparators COMP.sub.1 to COMP.sub.14, AND gates AGT.sub.1 to AGT.sub.15, an encoder ECD, and a control circuit TIMGEN. The plurality of resistors connected between the reference voltages VRT and VRB divides the difference of the reference voltages (VRT-VRB) to obtain a plurality of reference voltages VRT.sub.n and VRB.sub.n (n=1, 2, . . . , 14). The differential type voltage comparator COMP.sub.n compares the differential voltage of the reference signal (VRT.sub.n -VRB.sub.n) and the differential voltage of the differential input signal (AIN-XAIN) and sets the voltages of an output signal D and an inverted signal DX thereof in accordance with the result of comparison. The AND gates AGT.sub.1 to AGT.sub.15 output conversion codes in accordance with the result of comparison of the differential type voltage comparator. The encoder ECD converts the conversion codes from the AND gates AGT.sub.1 to AGT.sub.15 to for example binary codes.
A four-bit parallel type ADC shown in FIG. 1 has 15 voltage dividing resistors, 14 differential type voltage comparators, and 15 AND gates. An analog signal AIN, an inverted signal XAIN thereof, and a reference voltage V.sub.ref are input to each differential type voltage comparator. Note that the reference voltage V.sub.ref is the voltage of an intermediate level between the reference voltages VRT and VRB and, as shown in FIG. 2, is obtained by voltage division by the resistors R.sub.T and R.sub.B having the same resistance value connected in series between the reference voltages VRT and VRB. Further, the control circuit TIMGEN is provided in order to control the operation timing of the ADC.
The voltage comparators COMP.sub.1 to COMP.sub.14 constituting the parallel type ADC shown in FIG. 1 have the same configuration. Here, as a common example of them, an explanation will be made of the configuration and operation of a chopper type differential type voltage comparator COMP.
FIG. 3 is a circuit diagram of the configuration of a chopper type differential voltage comparator COMP constituted by switches 1 to 6, sampling use capacitor elements C.sub.S1 and C.sub.S2, a differential type operational amplifier 10, and a latch circuit 20.
The reference voltage VRT.sub.n and the analog signal AIN are selectively input to a node ND.sub.1 by the switches 1 and 2, respectively. The reference voltage VRB.sub.n and the inverted signal XAIN of the analog signal AIN are selectively input to a node ND.sub.2 by the switches 3 and 4, respectively. The sampling use capacitor element C.sub.S1 is connected between the node ND.sub.1 and the node ND.sub.3, and the sampling use capacitor element C.sub.S2 is connected between the node ND.sub.2 and the node ND.sub.4. The switch 5 is connected between the node ND.sub.3 and the input terminal of the reference voltage V.sub.ref, and the switch 6 is connected between the node ND.sub.4 and the input terminal of the reference voltage V.sub.ref. Capacitor elements C.sub.1 and C.sub.2 exist between the node ND.sub.3 and the node ND.sub.4 and a ground potential GND. Note that the capacitances of these capacitor elements are very small.
A voltage V- of the node ND.sub.3 is input to an inverted input terminal (-) of the operational amplifier 10, and a voltage V+ of the node ND.sub.4 is input to a non-inverted input terminal (+) of the operational amplifier 10. The output signal D of the operational amplifier 10, the output signal D of the inverted signal operational amplifier 10 thereof, and the inverted signal XD thereof are output via the latch circuit 20.
FIG. 4 is a waveform diagram of the operation of the chopper type differential voltage comparator shown in FIG. 3. The switches 1 and 3 are controlled in their conductive states by a clock signal SCKD.sub.2, and the switches 2 and 4 are controlled in their conductive states by a clock signal XSCK. Further, the switches 5 and 6 are controlled in their conductive states by a clock signal XSCKD.sub.1. The operation timing of the latch circuit 20 is controlled by a clock signal CCK.
The clock signal SCK is generated by the clock signal CLK. Its rising edge is the same as the clock signal CLK, and its trailing edge is delayed from the trailing edge of the clock signal CLK. The clock signals SCKD.sub.1 and SCKD.sub.2 are signals obtained by delaying the clock signal SCK.
In the chopper type differential voltage comparator shown in FIG. 3, the switches 1 and 3 are set to a conductive state when the clock signal SCKD.sub.2 is at a high level and are set to a non-conductive state when it is at a low level. The switches 2 and 4 are set to a conductive state when the inverted signal XSCK of the clock signal SCK is at the high level and are set to a non-conductive state when it is at the low level. The switches 5 and 6 are set to a conductive state when the inverted signal XSCKD.sub.1 of the clock signal SCKD.sub.1 is at the high level and are set to a non-conductive state when it is at the low level.
Below, an explanation will be made of the operation of the voltage comparator COMP by referring to FIGS. 3 and 4. During the period when the clock signal SCK is at the low level, the sampling operation (sample) is carried out. During the period when it is at the high level, a hold and comparison operation (hold & comp, hereinafter, simply referred to as a comparison operation) is carried out.
During the sampling operation, the switches 2, 4, 5, and 6 are set in a conductive state, and the switches 1 and 3 are set in a non-conductive state. The analog signal AIN and the reference voltage V.sub.ref are supplied to the two sides of the sampling use capacitor element C.sub.S1 whereby the sampling use capacitor element C.sub.S1 is charged to (AIN-V.sub.ref), and the inverted signal XAIN of the analog signal AIN and the reference voltage V.sub.ref are supplied to the two sides of the sampling use capacitor element C.sub.S2 whereby the sampling use capacitor element C.sub.S2 is charged to (XAIN-V.sub.ref).
During the comparison operation, the switches 1 and 3 are set in a conductive state, and the other switches are set in a non-conductive state. By this, the voltages V- and V+ of the node ND.sub.3 and node ND.sub.4 are individually represented by following equations: EQU V-=-C.sub.S (AIN-VRT.sub.n)/(C.sub.S +C.sub.1)+V.sub.ref (1) EQU V+=-C.sub.S (XAIN-VRB.sub.n)/(C.sub.S +C.sub.1)+V.sub.ref (2)
Here, assume that the capacitances of the sampling use capacitor elements C.sub.S1 and C.sub.S2 are the same, that is, C.sub.S, and the capacitances of the capacitor elements C.sub.1 and C.sub.2 are the same, that is. C.sub.1.
The differential voltage of the voltages V+ and V- is represented by the following equation: EQU (V+)-(V-)=(AIN-XAIN)-(VRT.sub.n -VRB.sub.n) (3)
The differential voltage of the voltages V+ and V- is amplified by the operational amplifier 10. The output signal D and the inverted signal XD thereof are latched by the latch circuit 20 at for example the rising edge of the clock signal CCK and output to an external unit.
In the differential type voltage comparator of the related art explained above, when the analog signal AIN and the inverted signal XAIN thereof are within the range of the reference voltages VRT and VRB as shown in FIG. 5, the reference voltage V.sub.ref becomes the same level as that of the DC component V.sub.C of the analog signal AIN, and the operational amplifier 10 uses the reference voltage V.sub.ref, that is, the DC component V.sub.C of the analog signal AIN, as the operation point. However, when the analog signal AIN and the inverted signal XAIN thereof are out of the range of the reference voltages VRT and VRB, that is, when the DC component V.sub.C of the analog signal AIN and the inverted signal XAIN thereof deviate from the center value V.sub.ref of the reference voltages VRT and VRB, the operation point of the operational amplifier 10 fluctuates during the sampling and comparison operations of the ADC. When the operation point becomes out of the input range of the operational amplifier 10, there is a problem that the voltage comparison is no longer correctly carried out and the precision of conversion of the ADC is deteriorated.
In order to solve this problem, it is necessary to shift the level of the analog signal AIN and the inverted signal XAIN thereof before the ADC input by using a full differential type operational amplifier as shown in FIG. 6. The full differential type operational amplifier in this case directly handles the input signal, therefore it is necessary to use one having excellent gain characteristics and frequency characteristics for the frequency of the input signal and the number of bits and conversion speed of the ADC. This causes an increase of the size of the circuit of the ADC and an increase of the costs. Further, the power consumption is increased due to the use of the high performance operational amplifier.